Search - fifo code

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[MiddleWare] controlpannel

Description: usb slavefifo 模式控制传输，控制接口，包括全部的源代码-usb slavefifo mode control transmission, control interface, including all the source code
Platform: | Size: 1927168 | Author: | Hits:

[Other] buffervhdl

Description: 电子EDA,VHDL语言设计8位的fifo数据缓冲器的vhdl源程序-E-EDA, VHDL language design 8-bit data buffer fifo VHDL source code
Platform: | Size: 1024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] 8_8_FIFO_VHDL

Description: 这是关于VHDL的8*8FIFO源代码，欢迎大家下载使用-This is about 8* 8FIFO The VHDL source code, welcomed everyone to download use
Platform: | Size: 1024 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] tx

Description: 自己编写的串口UART发送的Verilog模块。与FIFO连接，可以实现自动连续发送。-I have written serial UART to send the Verilog module. Connect with the FIFO, you can realize automatic continuous send.
Platform: | Size: 7168 | Author: YongZhiLi | Hits:

[Driver Develop] EZ-USBFX2Firmware

Description: 开发EZUSB的FX2的固件程序的源代码，开发环境是KEILC51，实现了批量传输。-Development EZUSB the FX2 firmware source code, development environment is KEILC51, realize the bulk transmission.
Platform: | Size: 123904 | Author: 韩胜军 | Hits:

[USB develop] async_fifo2_corrected

Description: FIFO的部分verilog代码，其余部分我会陆续上传，-FIFO part of Verilog code, I will continue the rest of the upload,
Platform: | Size: 136192 | Author: | Hits:

[OS program] hcq

Description: 能实现基本的三种页面算法，FIFO,OPT,LRU，自己的课程设计，代码较少，有待改进。-To achieve three basic page algorithm, FIFO, OPT, LRU, their curriculum design, code less room for improvement.
Platform: | Size: 9216 | Author: avaga | Hits:

[Embeded-SCM Develop] CY7C68013_FX2

Description: cypress fx2 firmware代码示例-cypress fx2 firmware code samples
Platform: | Size: 393216 | Author: kev | Hits:

[VHDL-FPGA-Verilog] ethernet_vhdl

Description: 千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.-Gigabit Ethernet controller. Can adjust FIFO, and the transmission rate, in the code stream control layer.
Platform: | Size: 30720 | Author: 王晶 | Hits:

[VHDL-FPGA-Verilog] vr_fifo

Description: 可预取的fifo 的fpga 设计代码，满足异步时钟的操作-Can prefetch the fifo of the FPGA design code, to meet the asynchronous clock operation
Platform: | Size: 573440 | Author: yy | Hits:

[OS Develop] pagechange

Description: 操作系统-页面置换算法（包括OPT、LRU、FIFO三种算法）-Operating system- page replacement algorithms (including OPT, LRU, FIFO three algorithms)
Platform: | Size: 10240 | Author: fish | Hits:

[Driver Develop] HIGH_SPEED_USB_To_ATA(IDE)Firmware

Description: HIGH_SPEED_USB_To_ATA(IDE)Firmware相关代码（EZ USB FX2芯片）-HIGH_SPEED_USB_To_ATA (IDE) Firmware related code (EZ USB FX2 chip)
Platform: | Size: 1654784 | Author: hui98765 | Hits:

[VHDL-FPGA-Verilog] fifo_VHDL

Description: FIFO的源代码，详细描述FIFO的工作原理和过程，用VHDL编写。-FIFO of the source code, a detailed description of the work of FIFO principle and process of preparation with VHDL.
Platform: | Size: 9216 | Author: 胡志敏 | Hits:

[OS program] os

Description: 操作系统：模拟磁盘调度算法课题要求：●建立相应的数据结构 ●在屏幕上显示磁盘请求的服务状况 ●时间的流逝可用下面方法模拟：（a）按键盘，没按一次可认为过了一个时间单位（b）响应WM_TIMER ●将一批磁盘请求的情况存磁盘文件，以后可以读出并重放 ●支持算法：FIFO，SSTF，SCAN，CSCAN，FSCAN -Operating Systems: simulation of disk scheduling algorithm subject requirements: ● the establishment of the corresponding data structure displayed on the screen ● disk status of the requested service ● time simulation can be used the following methods: (a) by the keyboard, not by one that had a time units (b) in response to a number of disk WM_TIMER ● request keep the disk files, then you can read and playback ● support algorithm: FIFO, SSTF, SCAN, CSCAN, FSCAN
Platform: | Size: 2051072 | Author: jiabin | Hits:

[Software Engineering] Asyn_FIFO_Design

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 228352 | Author: 刘强 | Hits:

[Software Engineering] multiplier_8bit

Description: 异步FIFO设计的说明文档，需要注意的问题以及源码（在文中有）。是标准的异步FIFO，可综合。-Asynchronous FIFO design documentation, as well as the need to pay attention to source code (in the text have). Is a standard asynchronous FIFO, can be integrated.
Platform: | Size: 46080 | Author: 刘强 | Hits:

[VHDL-FPGA-Verilog] FIFO_Buffer(verilog)

Description: 这是一个FIFO_Buffer的verilog代码.-This is a FIFO_Buffer the Verilog code.
Platform: | Size: 71680 | Author: 郑海伟 | Hits:

[Embeded Linux] program

Description: 工ARM＿LINUX的几个源代码，fork,pipe,fifo,及共享内存的实验源程序-Several workers ARM_LINUX source code, fork, pipe, fifo, and shared memory of the experimental source
Platform: | Size: 71680 | Author: yxh | Hits:

[Compress-Decompress algrithms] EZW

Description: EZW举例该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C －编码器数据结果定义和数据操作 FIFO.H FIFO.C －扫描方式定义：先入先出原则 LIST.H LIST.C －零树结构定义和操作 UNEZW.C － EZW解码器这里，读者重点要掌握的是EZW.C和LIST.C中的内容，充分理解零树的概念。 -EZW For the source code contains six files: EZW.H- EZW encoder header files EZW.C- EZW encoder document MATRIX2D.H MATRIX2D.C- encoder data definition and data manipulation FIFO.H FIFO.C-- scanning definition: the principle of FIFO LIST.H LIST.C- definition of zero-tree structure and operation of UNEZW.C- EZW decoder here, readers should have a focus EZW.C and LIST.C content, fully understand the zero- tree concept.
Platform: | Size: 11264 | Author: yang | Hits:

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